Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Frequently, these activities involve significant information processing. Traditionally the processing is performed by processors that include connections or pins for communicating general purpose input and output information associated with support functions. It is often desirable to be able to flexibly adjust a wide variety of support functions. However, flexibly interfacing with a wide variety of functions traditionally requires a significant number of connection pins which consume precious chip resources.
The ability to flexibly adjust a wide variety of functions usually facilitates desired processing characteristics. For example, it is usually desirable to process information rapidly. The amount of information and speed at which it is processed by a processor is determined by a variety of factors. A processor typically performs operations in a sequence of events (e.g., fetching, decoding and executing instructions), the timing of which are largely controlled by a clock signal. However, increasing the clock frequency is often limited by the characteristics of the transistors utilized to perform the processing. Higher voltages are usually used to sustain operations at a higher clock frequency, and higher clock frequencies and voltage supplies cause a processor to consume more power, thereby increasing the temperature of the processor. Continually running a processor at a high temperature stresses the semiconductor device and reduces long term reliability of the device. The ability to flexibly control the frequency, voltage and temperature a processor operates at is desirable.
Traditionally, flexibly interfacing with a variety of different general purpose functions usually requires a significant number of general purpose input/output pins (GPIOs). However, the number of GPIOs available in a typical system is usually limited and traditional attempts at expanding functionality by using passive components increases the complexity of manufacturing operations. The possible granularity and number of choices associated with traditional attempts utilizing passive components in an interface are also usually limited. Some conventional graphics processor unit (GPU) sub systems allocate some GPIOs to a specific support function to maintain BIOS compatibility in a family of boards based on a particular family of GPUs, even if the support function is not necessarily used in the system. For example, a GPIO may be assigned to a dynamic voltage changing support function which may not necessarily be used in all the possible implementations of a GPU system board. However, the GPIOs committed to the dynamic voltage changing support function can not usually be used for other purposes.
Generally, conventional processing systems usually dedicate N general purpose input/output pins to control each level of 2(N+1) decoded functional support (e.g., each of multiple voltage supply level). Some traditional systems utilize commutating resistors coupled to less than N general purpose input/output pins to simulate ‘N’ pins. This usually limits control to less than 2(N+1) levels of possible functional support. Utilizing passive commutating resistors in this conventional attempt to control support functions usually increases the complexity of manufacturing operations and still usually involves a significant number of pins to achieve desired flexibility.
FIG. 1 is a block diagram of a prior art general purpose input/output interface implementation. Central processing unit 110 has 4 general purpose input/output ports 111 through 114 controlled by port controllers 121 through 124 (e.g., control registers). The GPIOs 111 through 114 communicate 4 respective voltage level indication signals 141 through 144 to switcher 130. Switcher 130 controls a voltage supply (not shown) output and is capable of providing 32 different levels of control. The conventional general purpose input/output interface implementation requires 4 general purpose input/output pins to control 16 different switcher levels. The signal 145 is used to inform the switcher 130 to start at a single preset voltage level for CPU 110 during power on. Furthermore, even with four general purpose input/output pins, the prior art interface is usually not able to utilize the remaining 16 levels of possible voltage supply control otherwise available with switcher 130.
In addition to being limited in the number of levels a traditional systems can typically control, traditional systems also usually present indefinite timing characteristics which can be problematic. Traditional attempts at control of support operations are usually limited to progressive changes of one port or “level” at a time. For example, traditional attempts usually can not change from a level associated with GPIO port 111 directly to a level associated with GPIO port 114. Traditional control attempts usually involve a sequential change in which the controls (e.g., via port controller 122 and 123) for each intervening GPIO port (e.g., GPIO port 112 and 113) are altered before GPIO port 114. In addition, there is often a latency associated with multi-tasking events when modifying port controllers. A processor may change the values in port controller 121 an then perform other BIOS and/or operating system tasks before each change in a value of port controller 122, 123 and 124. In many cases the latency is indeterministic and slows implementation of desired CPU 110 voltage control level changes by switcher 130.
Greater flexibility in controlling support functions often facilitates the potential for implementation of more complicated functionality schemes. More complicated functionality schemes usually permit greater processing efficiency and optimization. Although it is important to provide for flexible general purpose operations, traditional attempts typically consume precious connections and expend valuable placement resources. Deciding whether to dedicate significant resources for a general purpose support function is usually very hard. It is difficult to predict the applications that will be utilized on a particular system with a great degree of certainty. Thus, conventional designs usually either expend significant chip resources on general purpose pins or leave out the advantageous features.